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24-bit, 312 ksps, 109 db sigma-delta adc with on-chip buffers and serial interface AD7764 rev. a information furnished by analog devices is believed to be accurate and reliable. however, no responsibility is assumed by analog devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. specifications subject to change without notice. no license is granted by implication or otherwise under any patent or patent rights of analog devices. trademarks and registered trademarks are the property of their respective owners. one technology way, p.o. box 9106, norwood, ma 02062-9106, u.s.a. tel: 781.329.4700 www.analog.com fax: 781.461.3113 ?2007-2009 analog devices, inc. all rights reserved. features high performance 24-bit -? adc 115 db dynamic range at 78 khz output data rate 109 db dynamic range at 312 khz output data rate 312 khz maximum fully filtered output word rate pin-selectable oversampling rate (64, 128, and 256) low power mode flexible spi fully differential modulator input on-chip differential amplifier for signal buffering on-chip reference buffer full band low-pass finite impulse response (fir) filter overrange alert pin digital gain correction registers power-down mode synchronization of multiple devices via sync pin daisy chaining applications data acquisition systems vibration analysis instrumentation functional block diagram refgnd v ref + buf v out a ? v out a+ v in + v in ? gnd mclk overrange dec_rate av dd 1 av dd 2 av dd 3 av dd 4 dv dd r bias sync reset/pwrdwn v in a+ v in a? fso sco sdi sdo fsi diff multibit - modulator reconstruction decimation fir filter engine AD7764 interface logic and offset and gain correction registers 06518-001 figure 1. table 1. related devices part no. description ad7760 2.5 msps, 100 db, parallel output on-chip buffers ad7762 625 ksps, 109 db, parallel output on-chip buffers ad7763 625 ksps, 109 db, serial output, on-chip buffers ad7765 156 ksps, 112 db, serial output, on-chip buffers ad7766 128/64/32 ksps, 8.5 mw, 109 db snr ad7767 128/64/32 ksps, 8.5 mw, 109 db snr general description the AD7764 is a high performance, 24-bit sigma-delta (-) analog-to-digital converter (adc). it combines wide input bandwidth, high speed, and performance of 109 db dynamic range at a 312 khz output data rate. with excellent dc specifications, the converter is ideal for high speed data acquisition of ac signals where dc data is also required. using the AD7764 eases the front-end antialias filtering requirements, simplifying the design process significantly. the AD7764 offers pin-selectable decimation rates of 64, 128, and 256. other features include an integrated buffer to drive the reference, as well as a fully differential amplifier to buffer and level shift the input to the modulator. an overrange alert pin indicates when an input signal has exceeded the acceptable range. the addition of internal gain and internal overrange registers makes the AD7764 a compact, highly integrated data acquisition device requiring minimal peripheral components. the AD7764 also offers a low power mode, significantly reducing power dissipation without reducing the output data rate or available input bandwidth. the differential input is sampled at up to 40 msps by an analog modulator. the modulator output is processed by a series of low-pass filters. the external clock frequency applied to the AD7764 determines the sample rate, filter corner frequencies, and output word rate. the AD7764 device boasts a full band on-board fir filter. the full stop-band attenuation of the filter is achieved at the nyquist frequency. this feature offers increased protection from signals that lie above the nyquist frequency being aliased back into the input signal bandwidth. the reference voltage supplied to the AD7764 determines the input range. with a 4 v reference, the analog input range is 3.2768 v differential, biased around a common mode of 2.048 v. this common-mode biasing can be achieved using the on-chip differential amplifier, further reducing the external signal conditioning requirements. the AD7764 is available in a 28-lead tssop package and is specified over the industrial temperature range of ?40c to +85c.
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AD7764 rev. a | page 2 of 3 2 table of contents features .............................................................................................. 1 applications ....................................................................................... 1 general description ......................................................................... 1 functional block diagram .............................................................. 1 revision history ............................................................................... 2 specifications ..................................................................................... 3 timing specifications .................................................................. 6 timing diagrams .......................................................................... 7 absolute maximum ratings ............................................................ 8 esd caution .................................................................................. 8 pin configuration and function descriptions ............................. 9 typical p erformance characteristics ........................................... 11 terminology .................................................................................... 15 theory of operation ...................................................................... 16 - modulation and digital filtering ..................................... 16 AD7764 antialias protection .................................................... 17 AD7764 input structure ................................................................ 18 on - chip differential amplifier ............................................... 19 modulator input structure ........................................................ 20 driving the modulator inputs directly ................................... 20 AD7764 interface ............................................................................ 21 reading data ............................................................................... 21 reading status and other registers ......................................... 21 writing to the AD7764 .............................................................. 21 AD7764 functionality .................................................................... 22 synchronization ...........................................................................22 overrange alerts .........................................................................22 power modes ................................................................................ 23 decimation rate pin ...................................................................23 daisy chaining ................................................................................ 24 reading data in daisy - chain mode ......................................... 24 writing data in daisy - chain mode ......................................... 25 clocking the AD7764 ..................................................................... 26 mclk jitter requirements ........................................................ 26 decoupling and layout information ............................................ 27 supply decoupling ......................................................................27 reference voltage filtering ........................................................ 27 differential amplifier components ......................................... 27 layout considerations ................................................................ 27 using the AD7764 ....................................................................... 28 bias resistor selection ................................................................ 28 AD7764 registers ............................................................................ 29 control register ...........................................................................29 status register ..............................................................................29 g ain register address 0x0004 ................................................30 overrange register address 0x0005 ...................................... 30 outline dimensions ........................................................................31 ordering guide ............................................................................ 31 revision history 11/0 9 r ev . 0 to rev. a ch anges to table 2 ............................................................................ 4 changes to table 3 ............................................................................ 6 changes t o table 4 ............................................................................ 8 changes to typical performance characteristics section , introductory text ............................................................................ 11 changes to - modulation and digital filtering section ....... 16 added AD7764 antialias protection section ............................. 17 changes to figure 35 ...................................................................... 19 added driving the modulator input s direc tly section , including figure 39 and figure 40, renumbered subsequent figures ...... 20 changes to synchronization section , added figure 41 .............22 changes to power modes section , added figure 44 ..................23 changes to example 2 section ....................................................... 26 change s to using the AD7764 section ......................................... 28 6/07 revision 0: initial version
AD7764 rev. a | page 3 of 3 2 specifications av dd 1 = dv dd = 2.5 v, av dd 2 = av dd 3 = av dd 4 = 5 v, v ref + = 4.096 v, mclk amplitude = 5 v, t a = 25c, normal po wer mode, using the on - chip amplifier with components , as shown in the optimal row in table 7 , unless otherwise noted . 1 parameter table 2. test conditions/comments specif i cation unit dynamic performance decimate 256 normal power mode mclk = 40 mhz, odr = 78.125 khz, f in = 1 khz sine wa ve dynamic range modulator inputs shorted 115 db typ 110 db min differential a mplifier inputs shorted 113.4 db typ signal - to - noise ratio (snr) 2 in put amplitude = ?0.5 db 109 db typ 106 db min spurious - free dynamic range (sfdr) non harmonic 130 dbfs typ total harmonic distortion (thd) input a mplitude = ? 0.5 db ? 105 db typ input a mplitude = ?6 db ? 103 db typ input a mplitude = ? 60 db ? 71 db typ low power mode mclk = 40 mhz, odr = 78.125 khz, f in = 1 khz sine wav e dynamic range modulator inputs shorted 113 db typ 110 db min differential a mplifier inputs shorted 112 db typ signal - to - noise ratio (snr) 2 i nput a mplitude = ? 0.5 db 109 db typ 10 6 db min total harmonic distortion (thd) input a mplitude = ? 0.5 db ? 105 db typ input a mplitude = ?6 db ? 111 db typ input a mplitude = ?6 db ? 100 db max input a mplitude = ? 60 db ? 76 db typ decimate 128 normal power mode m clk = 40 mhz, odr = 156.25 khz, f in = 1 khz sine w ave dynamic range modulator inputs shorted 112 db typ 108 db min differential amplifier inputs shorted 110.4 db typ signal - to - noise ratio (snr) 2 107 db typ 1 05 db min spurious - free dynamic range (sfdr) non harmonic 130 dbfs typ total harmonic distortion (thd) input a mplitude = ? 0.5 db ? 105 db typ input amplitude = ?6 db ? 103 db typ intermodulation distortion (imd) input a mplitude = ?6 db, f in a = 50.3 k hz, f in b = 47.3 k hz s econd - order terms ? 117 db typ third - order terms ? 108 db typ low power mode mclk = 40 mhz, odr = 156.25 khz, f in = 1 khz sine w ave dynamic range modulator inputs shorted 110 db typ 109 db min differential a mplifier inputs shorted 109 db typ signal - to - noise ratio (snr) 2 input a mplitude = ? 0.5 db 107 db typ 105 db min total harmonic distortion (thd) input a mplitude = ? 0.5 db ? 105 db typ input a mplitude = ?6 db ? 111 db typ input amplitude = ?6 db ?100 db max intermodulation distortion (imd) input amplitude = ?6 db, f in a = 50.3 khz, f in b = 47.3 khz second - order terms ? 134 db typ third - order terms ? 110 db typ
AD7764 rev. a | page 4 of 32 parameter test conditions/comments specif i cation unit decimate 64 normal power mode mclk = 40 mhz, odr = 312.5 khz, f in = 1 khz sine w ave dynamic range modulator inputs shorted 109 db typ 105 db min differential a mplifier inputs sh orted 107.3 db typ signal - to - noise ratio (snr) 2 104 db typ 102.7 db min spurious - free dynamic range (sfdr) non harmonic 130 dbfs typ total harmonic distortion (thd) input a mplitude = ? 0.5 db ? 105 db typ input a mp litude = ?6 db ? 103 db typ intermodulation distortion (imd) input a mplitude = ?6 db, f in a = 100.3 k hz, f in b = 97.3 k hz second -o rder terms ? 118 db third -o rder terms ?1 08 db low power mode dynamic range modulator inputs shorted 106 db typ 1 05 db min differential a mplifier inputs shorted 105.3 signal - to - noise ratio (snr) 2 input a mplitude = ? 0.5 db 103 db typ 102 db min spurious - free dynamic range (sfdr) non harmonic 110 dbfs typ total harmonic distor tion (thd) input a mplitude = ? 0.5 db ? 105 db typ input a mplitude = ?6 db ? 111 db typ ? 100 db max dc accuracy resolution guaranteed monotonic to 24 bits 24 bits integral nonlinearity normal p ower mode 0.0036 % typ low p ower mode 0.0014 % typ z ero error normal p ower mode 0.006 % typ 0.03 % max including on- chip a mplifier 0.04 % typ low p ower mode 0.002 % typ 0.024 % max gain error 0.018 % typ inclu ding on - chip a mplifier 0.04 % typ zero error drift 0.00006 %fs/c typ gain error d rift 0.00005 %fs/c typ digital filter characteristics pass -b and ripple 0. 1 db typ pass b and 3 ?1 db frequency odr 0.4016 khz ?3 db bandwidth 3 odr 0.4096 khz stop b and 3 beginning of s top band odr 0.5 khz stop - band attenuation decimate 64 and d ecimate 128 modes ? 120 db typ decimate 256 ? 11 5 db typ group delay decimate 64 mclk = 40 mhz 89 s typ decimate 128 mclk = 40 mhz 17 7 s typ decimate 256 mclk = 40 mhz 358 s typ analog input differential input voltage modulator input pins: v in + ? v in ? , v ref + = 4. 096 v 3.2 768 v p -p input capacitance at on - chip differential amplifier inputs 5 pf typ at m odulator inputs 29 pf typ
AD7764 rev. a | page 5 of 32 parameter test conditions/comments specif i cation unit reference input/output v ref + input voltage av dd 3 = 5 v 5% 4.096 v v ref + i nput dc leakage current 1 a max v ref + input capaci tance 5 pf typ digital input/output mclk input amplitude 2 .25 to 5 .25 v input capacitance 7.3 pf typ input leakage current 1 a/pin max v inh 0.8 dv dd v min v in l 0.2 dv dd v m ax v oh 4 2.2 v min v ol 0.1 v max on- chip differential a mplifier input i mpedance >1 m bandwidth for 0.1 db flatness 125 khz common - mode input voltage voltage range at input pins : v in a+ an d v in a? ? 0.5 to + 2.2 v common - mode output voltage on - chip d ifferential a mplifier pins : v out a + and v out a? 2.048 v power requirements av dd 1 (modulator supply) 5% 2.5 v av dd 2 (general supply) 5% 5 v av dd 3 (differential amplifier supply) 5% 5 v min/ max av dd 4 (ref buffer supply) 5% 5 v min/max dv dd 5% 2.5 v normal power mode ai dd 1 ( modulator) 19 ma typ ai dd 2 (general) 5 mclk = 40 mhz 13 ma typ ai dd 3 (differential amplifier) av dd 3 = 5 v 10 ma typ ai dd 4 (reference buffer) av dd 4 = 5 v 9 ma t yp di dd 5 mclk = 40 mhz 37 ma typ low power mode ai dd 1 (modulator) 10 ma typ ai dd 2 (general) 5 mclk = 40 mhz 7 ma typ ai dd 3 (differential amplifier) av dd 3 = 5 v 5.5 ma typ ai dd 4 (re ference buffer) av dd 4 = 5 v 5 ma typ di dd 5 mclk = 40 mhz 20 ma typ power dissipation normal power mode mclk = 40 mhz, decimate 64 300 mw typ 371 mw max low power mode mclk = 40 mhz, decimate 64 160 mw typ 215 mw max power - down mode 6 pwrdwn 1 held logic low mw typ 1 see the terminology section. 2 snr specifica tions in decibels are referred to a full - scale input, fs. tested with an input signal at 0.5 db below full scale, unless otherwise specified. 3 output data rate (odr) = [(mclk/2)]/decimation rate. that is, the maximum odr for AD7764 = [(40 mhz)/2)/64] = 31 2.5 khz . 4 tested with a 400 a load current. 5 tested at mclk = 40 mhz. this current scales linearly with the mclk frequency applied. 6 tested at 125c.
AD7764 rev. a | page 6 of 32 timing specification s av dd 1 = dv dd = 2.5 v, av dd 2 = av dd 3 = av dd 4 = 5 v, v ref + = 4.096 v, t a = 25c, c l oa d = 25 pf. table 3. parameter limit at t min , t max unit description f mclk 500 k hz min applied master clock frequency 40 mhz max f iclk 250 khz min inter nal modulator clock deriv ed from mclk 20 mhz max t 1 1 t iclk typ sco high pe riod t 2 1 t iclk typ sco low per iod t 3 1 ns typ sco rising e dge to fso falling edge t 4 2 ns typ data a ccess time, fso falling edge to data active t 5 8 ns max msb data access time, sdo active to sdo valid t 6 40 ns min data hold time (sdo valid to sco r ising e dge) t 7 9.5 ns m ax data access time (sco rising edge to sdo valid) t 8 2 ns typ sco rising edge to fso rising edge t 9 32 t sco max fso low pe riod t 10 12 ns min set up time from fsi falling edge to sco falling edge t 11 1 t sco min fsi l ow p eriod t 12 1 32 t sco max fsi l ow p eriod t 13 12 ns min sdi set up time for the first data bit t 14 12 ns min sdi set up time t 15 0 ns max sdi hold time t r min 1 t mclk min minimum time for a va lid reset pulse t r hold 5 ns min minimum time between the mclk rising edge and reset rising edge t r setup 5 ns min minimum time between the reset rising edge and mclk rising edge t s min 4 t mclk mi n minimum time for a valid sync pulse t s h old 5 ns min minimum time between the mclk falling edge and sync rising edge t s setup 5 ns min minimum time between the sync rising edge and mclk falling edg e 1 this is the maximum time fsi can be held low when writing to an individual dev ice (a device that is not daisy - chained).
AD7764 rev. a | page 7 of 32 timing diagrams d22 d23 d21 d20 d19 d1 d0 st4 st3 st2 st1 st0 0 0 0 sco (o) fso (o) sdo (o) t 1 t 9 32 t sco t 2 t 8 t 3 t 4 t 5 t 7 t 6 06518-002 figure 2 . serial read timing diagram ra15 ra14 ra13 ra12 ra11 ra10 ra9 ra8 ra1 ra0 d15 d14 d1 d0 sco (o) fsi (i) sdi (i) t 12 t 1 t 10 t 13 t 14 t 15 t 11 t 2 06518-003 figure 3 . AD7764 register write status register contents [31:16] don?t care bits [15:0] sco (o) sdo (o) fsi (i) sdi (i) fso (o) 8 t sco next data read following the write to control register control register addr (0x0001) control register instruction 06518-004 figure 4 . AD7764 status register r ead c ycle
AD7764 rev. a | page 8 of 32 absolute maximum rat ings t a = 25c, unless otherwise noted . table 4. parameter rating av dd 1 to gnd ?0.3 v to +2.8 v av dd 2, av dd 3, av dd 4 to gnd ?0.3 v to +6 v dv dd to gnd ?0.3 v to +2.8 v v in a+, v in a? to gnd 1 ?0.3 v to +6 v v in +, v in ? to gnd 1 ?0.3 v to +6 v digital i nput v oltage to gnd 2 ?0.3 v to +2.8 v v ref + to gnd 3 ?0.3 v to +6 v input current t o any pin e xcept s upplies 4 10 ma operating t emperature r ange commercial ? 40c to +85c storage temperature r ange ? 65c to +150c junction t emperature 150c tssop package ja thermal i mpedance 143 c/w jc thermal i mpedance 45 c/w lead temperature , s oldering vapor p hase (60 sec ) 215c infrared (15 sec ) 220c esd 1 kv 1 absolute maximum voltage for v in ? , v in + , v in a? , and v in a+ is 6.0 v or av dd 3 + 0.3 v, whichever is lower. 2 absolute maximum voltage on digital input is 3.0 v or dv dd + 0.3 v, w hichever is lower. 3 absolute maximum voltage on v ref + input is 6.0 v or av dd 4 + 0.3 v, whichever is lower. 4 transient currents of up to 100 ma do not cause scr latch - up. stresses above those listed under absolute maximum ratings may cause permanent damage to the device. this is a stress rating only; functional operation of the device at these or any other conditions above those listed in the operational sections of this specification is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. esd caution
AD7764 rev. a | page 9 of 32 pin configuration and function descriptions 1 2 3 4 5 6 7 8 9 10 11 12 13 14 28 27 26 25 24 23 22 21 20 19 18 17 16 15 v out a+ v in a+ v out a? av dd 2 v in + v in ? v in a? v ref + refgnd av dd 4 r bias agnd1 av dd 1 agnd3 overrange sco fsi sdo fso av dd 2 agnd2 mclk sync sdi reset/pwrdwn dv dd dec_rate av dd 3 AD7764 top view (not to scale) 06518-005 figure 5 . pin configuration table 5 . pin function descriptions pin n o. mnemonic descripti on 24 av dd 1 2.5 v power s upply for m odulator. t his pin should be decoupled to agnd1 ( p in 23 ) with a 100 nf capacitor. 7 and 21 av dd 2 5 v power s upply. pin 7 should be decoup led to agnd3 (p in 8) with a 100 nf capacitor. pin 21 should be decoupled to agnd1 (p in 23) with a 100 nf capacitor. 28 av dd 3 3.3 v to 5 v p ower supply for d ifferential amplifier . this pin should be decoupled to the ground plane with a 100 nf capacitor. 25 av dd 4 3.3 v to 5 v power s upply for reference b uffer. this pin should be decoupled to agnd1 (p in 23) with a 100 nf capacitor. 17 dv dd 2.5 v p ower s upply for d igital circuitry and fir f ilter. this pin should be decoupled to the ground plane with a 100 nf capacitor. 22 r bias bias current setting p in. this pin must be decoupled to t he ground plane . for more details, see the bias resistor selection section . 23 agnd1 power supply g round for a nalog c ircuitry. 20 agnd2 power supply ground for analog circuitry. 8 agnd3 power supply ground for analog circuitry . 26 refgnd reference ground. ground connection for the reference voltage. 27 v ref + reference input. 1 v in a? negative input to differential amplifier. 2 v out a+ positive output from differential amplifier. 3 v in a+ positive input to differential amplifier. 4 v out a? negative output from differential amplifier. 5 v in ? negative input to the modulator. 6 v in + po sitive input to the modulator. 9 overrange over range pin . this pin outputs a logic high to indicate that the user has applied an analog input that is approaching the limit of the analog input to the modulator. 10 sco serial clock out. this clock signal is derived from the internal iclk signal. the frequency of this clock is equal to iclk. see the clocking the AD7764 section for further details. 11 fso frame sync out. this signal frames the serial data output and is 32 sco periods wide. 12 sdo serial data out. data and s tatus are output on this pin during each serial transfer. each bit is clocked out on an sco rising edge and is valid on the falling edge . see the AD7764 interface sect ion for further details. 13 sdi serial data in. the first data bit (msb) must be valid on the next sco falling edge after the fsi event is latched. thirty - two bits are required for each write; the first 16 - bit word contains the device an d register address, and the second word contains the data. see the AD7764 interface section for further details.
AD7764 rev. a | page 10 of 32 pin n o. mnemonic descripti on 14 fsi frame sync input. the status of this pin is checked on the falling edge of sco. if this pin is low , then the first data bit is latched in on the next sco falling edge. see the AD7764 interface section for further details. 15 sync synchronization input. a falling edge on this pin resets the internal fi lter. this can be used to synchronize multiple devices in a system. see the synchroniz ation section for further details. 16 reset / reset/power -d own pin . when a logic low is sensed on t his pin, the part is powered down and all internal circuitry is reset. pwrdwn 19 mclk master clock input. a low jitter digital clock must be applied to this pin. the output data rate depend s on the frequency of this clock. see the clocking the AD7764 s ection for more details. 18 dec_rate decimation rate. this pin selects one of the three decimation rate modes. when 2.5 v is applied to this pin, a decimation rate of 64 is selected. a decimation rate of 128 is selected by leaving the p in floating. a decimation rate of 256 is selected by setting the pin to ground.
AD7764 rev. a | page 11 of 32 typical performance characteristics av dd 1 = dv dd = 2.5 v, av dd 2 = av dd 3 = av dd 4 = 5 v, v ref + = 4.096 v, mclk amplitude = 5 v, t a = 25c. linearity plots measured to 16 - bi t accuracy. input signal reduced to avoid modulator overload and digital clipping; f ast fourier transforms (ffts) of ? 0.5 db tones are generated from 262,144 samples in normal power mode. all other ffts are generated from 8192 samples . 0 ?25 ?50 ?75 ?100 ?125 ?150 ?175 0 50k 100k 156.249k amplitude (db) frequency (hz) 06518-006 figure 6 . normal power mode , fft, 1 k hz, ? 0.5 db input t one, 64 d ecimation rate 0 ?25 ?50 ?75 ?100 ?125 ?150 ?175 0 20k 40k 60k 78.124k amplitude (db) frequency (hz) 06518-007 figure 7. normal powe r mode , fft,1 k hz, ? 0.5 db input t one, 128 d ecimation rate 0 ?25 ?50 ?75 ?100 ?125 ?150 ?175 0 10k 20k 30k 39.062k amplitude (db) frequency (hz) 06518-008 figure 8 . normal p ower mode , f ft, 1 khz, ?0.5 db input tone, 256 d ecimation rate 0 150k 125k 100k 75k 50k 25k amplitude (db) frequency (hz) 06518-212 0 ?25 ?50 ?75 ?100 ?125 ?150 ?175 figure 9. low power mode, fft, 1 khz, ?0.5 db input tone, 64 decimation rate 0 10k 20k 30k 40k 50k 60k 70k amplitude (db) frequency (hz) 06518-211 0 ?25 ?50 ?75 ?100 ?125 ?150 ?175 figure 10 . low power mode, fft, 1 khz, ?0.5 db input tone, 128 d ecimation rate 0 5k 10k 15k 20k 25k 30k 35k amplitude (db) frequency (hz) 06518-210 0 ?25 ?50 ?75 ?100 ?125 ?150 ?175 figure 11 . low power mode, fft, 1 khz, ?0.5 db input tone, 256 decimation rate
AD7764 rev. a | page 12 of 32 0 100k 150k 50k amplitude (db) frequency (hz) 06518-200 0 ?25 ?50 ?75 ?100 ?125 ?150 ?175 figure 12 . normal power mode, fft, 1 khz, ?6 db input tone, 64 decimation rate 0 50k 75k 25k amplitude (db) frequency (hz) 06518-201 0 ?25 ?50 ?75 ?100 ?125 ?150 ?175 figure 13 . normal power mode, fft, 1 khz, ?6 db input tone, 128 decimation rate 0 35k 30k 25k 20k 15k 10k 5k amplitude (db) frequency (hz) 06518-202 0 ?25 ?50 ?75 ?100 ?125 ?150 ?175 figure 14 . normal power mode, fft, 1 khz, ?6 db input tone, 256 decimation rate 0 100k 150k 50k amplitude (db) frequency (hz) 06518-203 0 ?25 ?50 ?75 ?100 ?125 ?150 ?175 figure 15 . low power mode, fft , 1 khz, ? 6 db input tone, 64 decimation rate 0 50k 75k 25k amplitude (db) frequency (hz) 06518-204 0 ?25 ?50 ?75 ?100 ?125 ?150 ?175 figure 16 . low power mode, fft, 1 khz, ?6 db input tone, 128 decimation rate 0 35k 30k 25k 20k 15k 10k 5k amplitude (db) frequency (hz) 06518-205 0 ?25 ?50 ?75 ?100 ?125 ?150 ?175 figure 17 . low power mode, fft, 1 khz, ?6 db input tone, 256 decimation rate
AD7764 rev. a | page 13 of 32 40 35 30 25 20 15 10 5 0 0 10 20 30 40 5 15 25 35 current (ma) mclk frequency (mhz) dv dd av dd 2 av dd 1 av dd 3 av dd 4 06518-010 figure 18 . normal power mode, current consumption vs. mclk frequency, 64 decimation rate 40 35 30 25 20 15 10 5 0 0 10 20 30 4540 5 15 25 35 current (ma) mclk frequency (mhz) dv dd av dd 2 av dd 3 av dd 4 av dd 1 06518-114 figure 19 . normal power mode, current consumption vs. mclk frequency, 128 decimation rate 40 35 30 25 20 15 10 5 0 0 10 20 30 40 5 15 25 35 current (ma) mclk frequency (mhz) av dd 1 dv dd av dd 2 av dd 3 av dd 4 06518-112 figure 20 . normal power mode, current consumption vs. mclk frequency, 256 decimation rate 25 20 15 10 5 0 0 10 20 30 4540 5 15 25 35 current (ma) mclk frequency (mhz) av dd 4 av dd 3 av dd 1 dv dd av dd 2 06518-011 f igure 21 . low power mode, current consumption vs. mclk frequency, 64 decimation rate 25 20 15 10 5 0 0 10 20 30 4540 5 15 25 35 current (ma) mclk frequency (mhz) dv dd av dd 2 av dd 4 av dd 1 av dd 3 06518-115 figure 22 . low power mode, current consumption vs. mclk frequency, 128 decimation rate 20 18 16 14 12 10 8 6 4 2 0 0 10 20 30 40 5 15 25 35 current (ma) mclk frequency (mhz) dv dd av dd 2 av dd 3 av dd 4 av dd 1 06518-113 figure 23 . low power mode, current consumption vs. mclk frequency, 256 decimation rate
AD7764 rev. a | page 14 of 32 2.0 ?2.0 ?1.5 ?1.0 ?0.5 0 0.5 1.0 1.5 6k 55k 59,535 10k 15k 20k 25k 30k 35k 40k 45k 50k dnl (lsb) code 06518-208 figure 24 . dnl plot 0.00300 ?0.00300 ?0.00225 ?0.00150 ?0.00075 0 0.00075 0.00150 0.00225 6k 55k 59,535 10k 15k 20k 25k 30k 35k 40k 45k 50k inl (%) 16-bit code scaling 06518-206 ?40c +25c +85c figure 25. n ormal power mode inl 110 109 108 107 106 105 104 103 102 0 64 128 192 256 low snr snr (db) decimation rate normal snr 06518-009 figure 26 . normal and low power mode, snr vs. decimation rate, 1 khz, ?0.5 db input tone 0 ?20 ?40 ?60 ?80 ?100 ?120 ?140 ?160 ?180 0 78,124 60k 40k 20k amplitude (db) frequency (hz) 06518-209 figure 27. normal power mode, imd, f in a = 49.7 k hz, f in b = 50.3 khz, 50 khz center frequency, 128 decimation rate 6k 55k 59,535 10k 15k 20k 25k 30k 35k 40k 45k 50k inl (%) 16-bit code scaling 06518-207 ?40c +25c +85c 0. 003225 0. 003000 0. 00225 0. 00150 0. 00075 0 ?0.0001 2 figure 28 . low power mode i nl
AD7764 rev. a | page 15 of 32 terminology signal - to - noise ratio (snr) t he ratio of the rms value of the actual input signal to the rms sum of all other spectral components below the nyquist fre - quency, excluding harmonics and dc. the value for snr is expressed in decibels (db) . total harmonic distortion (thd) the ratio of the rms sum of harmonics to the fundamental. for the AD7764, it is defined as ( ) 1 6 54 32 v vvvvv thd 22222 log20 db ++++ = where: v 1 is the rms amplitude of the fundamental. v 2 , v 3 , v 4 , v 5 , and v 6 are the rms amplitudes of the se cond to the sixth harmonics. nonharmonic spurious - free dynamic range (sfdr) t he ratio of the rms signal amplitude to the rms value of the peak spurious spectral component, excluding harmonics. dynamic range t he ratio of the rms value of the full scale to the rms noise measured with the inputs shorted together. the value for dynamic range is expressed in decibels. intermodulation distortion with inputs consisting of sine waves at two frequencies, fa and fb, any active device with nonlinearities creates di stortion products at sum and difference frequencies of mfa nfb, where m, n = 0, 1, 2, 3, and so on. intermodulation distortion terms are those for which neither m nor n is equal to 0. for example, the second - order terms include (fa + fb) and (fa ? fb), while the third - order terms include (2fa + fb), (2fa ? fb), (fa + 2fb), and (fa ? 2fb). the ad776 4 is tested using the ccif standard, where two input frequencies near the top end of the input bandwidth are used. in this case, the second - order terms are u sually distanced in frequency from the original sine waves, and the third - order terms are usually at a frequency close to the input frequencies. as a result, the second - and third - order terms are specified separately. the calculation of the intermodulation distortion is as per the thd specification, where it is the ratio of the rms sum of the individual distortion products to the rms amplitude of the sum of the fundamentals expressed in decibels . integral nonlinearity (inl) t he maximum deviation from a str aight line passing through the endpoints of the adc transfer function. differential nonlinearity (dnl) t he difference between the measured and the ideal 1 lsb change between any two adjacent codes in the adc. zero error t he difference between the ideal mid scale input voltage (when both inputs are shorted together) and the actual voltage producing the midscale output code. zero error drift t he change in the actual zero error value due to a temperature change of 1c. it is expressed as a percentage of full sc ale at room temperature. gain error the first transition (from 100000 to 100001) should occur for an analog voltage 1/2 lsb above the nominal negative full scale. the last transition (from 011110 to 011111) should occur for an analog voltage 1 1/2 lsb below the nominal full scale. the gain error is the deviation of the difference between the actual level of the last transition and the actual level of the first transition, from the difference between the ideal levels. gain error drift t he change in the actual gain error value due to a temperature change of 1c. it is expressed as a percentage of full scale at room temperature.
AD7764 rev. a | page 16 of 32 theory of operation the AD7764 features an on - chip fully differential amplifier to feed the - modulator pins, an on -chi p reference buffer , and a fir filter block to perform the required digital filter ing o f the - modulator output. using this - conversion technique with the added digital filtering, the analog input is converted to an equivalent digital word. - m odul ation and digital f iltering the input waveform applied to the modulator is sampled , and an equivalent digital word is output to the digital filter at a r ate equal to iclk . by employing over sampling , the quantization noise is spread across a wide bandwidth from 0 to f iclk . this means that t he noise energy contained in the signal band of interest is reduced ( see figure 29 ). to further reduce the quantization noise, a high - order modulator is emplo yed to shape the noise spectrum so t hat most of the noise energy is shifted out of the signal band ( see figure 30 ). quantization noise f iclk /2 band of interest 06518-012 figure 29. - adc, quantization noise f iclk /2 noise shaping band of interest 06518-013 figure 30 . - adc, noise shaping f iclk /2 band of interest digital filter cutoff frequency 06518-014 figure 31 . - adc , digital filter cutoff frequency the digital filtering that follows the modulator removes the large out - of - band quantization noise ( see figure 31 ) while also reducing the data rate from f iclk at the input of the filter to f iclk /64 or less at the output of the filter, depending on the decimation r ate used. the AD7764 employs three fir filters in series. by using different combinations of decimation ratios, data can be obtained from the AD7764 at thr ee data rates. the first filter receives data from the modulator at iclk mhz where it is decimated 4 to output data at (iclk/4) mhz . the second filter allows the decimation rate to be chosen from 8 to 32 . the third filter has a fixed decimation rate of 2. table 6 shows some characteristics of the digital fi ltering where iclk = mclk /2. the group delay of the filter is defined to be the delay to the center of the impulse response and is equal to the compu - tation plus the filter del ays. the delay until valid data is available (the filter - settle status bit is set) is approximately twice the filter delay plus the computation delay. this is listed in terms of mclk periods in table 6 . 0 ?160 ?140 ?120 ?100 ?80 ?60 ?40 ?20 0 300 250 200 150 100 50 amplitude (db) frequency (khz) pass-band ripple = 0.05db ?0.1db frequency = 125.1khz ?3db frequency = 128khz stop band = 156.25khz 06518-015 figure 32 . filter frequency response (312.5 khz odr) table 6 . configuration w ith default filter iclk frequency decimation rate data state computation delay filter delay sync pass - band bandwidth to f i lt er - settle out put data rate (odr) 20 mhz 64 fully filtered 2.25 s 87.6 s 7122 t mclk 125 khz 312.5 khz 20 mhz 128 fully filtered 3.1 s 174 s 14217 t mclk 62.5 khz 156.25 khz 20 mhz 256 fully filtered 4.65 s 346.8 s 27895 t mclk 31.25 khz 78.125 khz 12.28 8 mhz 64 fully filtered 3.66 s 142.6 s 7122 t mclk 76.8 khz 192 khz 12.288 mhz 128 fully filtered 5.05 s 283.2 s 14217 t mclk 38.4 khz 96 khz 12.288 mhz 256 fully filtered 7.57 s 564.5 s 27895 t mclk 19.2 khz 48 khz
AD7764 rev. a | page 17 of 32 AD7764 antialias pro te ction the decimation of the AD7764, along with its counterparts in the ad776x family, namely the ad7760 , ad7762 , ad7763 , and ad7765 , provides top of the range antialias protection. the decimation filter of the AD7764 features more than 115 db of attenuation across the full stop band, which ranges from the nyquist frequency, namely odr/2, up to iclk C odr/2 (where odr is the output data rate). starting the stop band at the nyquist frequency prevents any signal component above nyquist (and up to iclk C odr/2) from aliasing into the desired signal bandwidth. figure 32 shows the frequency response of the decimation filter when the AD7764 is operated with a 40 mhz mclk in decimate 128 mode. note that the first stop - band frequency occurs at nyquist. the frequency response of the filter scales with both th e decimation rate chosen and the mclk frequency applied. when using low power mode, the modulator sample rate is mclk/4. taking as an example the AD7764 in normal power and in decimate 128 mode, the first possible alias frequency is at the iclk frequency minus the pass band of the digital filter (see figure 33 ). nyquist = 78khz odr = 156khz modulator sampling rate = mclk/2 = 20mhz first alias point 20mhz to 78khz simplfies antialias filter roll-off required digital filter response frequency (hz) digital filter response image noise shaping amplitude (db) no aliasing of signals into passband around nyquist frequency 06518-213 figure 33 . antialias example using the AD7764 in normal mode, decimate 128 using mclk/2 = iclk = 20 mhz
AD7764 rev. a | page 18 of 32 AD7764 input structu re the AD7764 requires a 4.096 v input to the reference pin , v ref +, supplied by a high precision reference , such as the adr444 . becaus e the input to the device s - modulator is fully differential , the effective differential reference range is 8.192 v. v192.8096.42 )( == + diff ref v as is inherent in - modulators , only a certain portion of this full reference may be used. with the AD7764 , 80% of the full differential r eference can be applied to the modulators differ - ential inputs. v5536.68.0v192.8 _ == fullscale input modulator this means that a maximum of 3.2768 v p-p full - scale can be applied to each of the AD7764 modul at or inputs (p in 5 and p in 6), with the AD7764 being specified with an input ? 0.5 db down from full scale (? 0.5 dbfs) . the AD7764 modulator inputs must have a common - mode input of 2.048 v. figure 34 shows the relative scaling between the differential voltages applied to the modulator pins and the respecti ve 24 - bit twos complement digital output s. 06518-120 input to modulator pin 5 and pin 6 v in C and v in + v in + = 3.6855v 0111 1111 1111 1111 1111 1111 0000 0000 0000 0000 0000 0000 +3.2768v = modulator full-scale = 80% of 4.096v 80% of 4.096v = modulator full-scale = C3.2768v +4.096v C4.096v v in C = 0.4105v v in + = 2.048v v in C = 2.048v v in C = 3.6855v v in + = 0.4105v 1000 0000 0000 0000 0000 0000 0111 1000 1101 0110 1111 1101 1000 0111 0010 1001 0000 0010 C0.5dbfs input C0.5dbfs input overrange region overrange region digital output on sdo pin 0000 0000 0000 0000 0000 0001 1111 1111 1111 1111 1111 1111 twos complement digital output input voltage (v) figure 34. AD7764 scaling: modulator i nput v oltage vs. digital output c ode
AD7764 rev. a | page 19 of 32 on - chip differential am plifier the AD7764 contains an on - board differential amplifier that is recommended t o drive the modulator input pins. pin 1, pin 2, pin 3, and pin 4 on the AD7764 are the diffe rential input and output pins of the amplifier. t he external components , r in , r fb , c fb , c s , and r m , are placed around p in 1 through pin 6 to create the recommended configuration. to achieve the specified performance , the differential amplifier should be c onfigured as a first - order anti alias filter, as shown in figure 35 , using the component values listed in table 7 . the inputs to the differential amplifier are then routed through th e external component network before being applied to the mod - ulator inputs , v in ? and v in + ( pin 5 and pin 6) . using the optimal values in the table as an example yields a 2 5 db attenuation at the first alias point of 19. 6 mhz . r fb c fb r in r in r m r m c s c m v in ? v in + 06518-024 diff amp r fb c fb a b 1 3 2 4 5 6 v in a? v in a+ v out a+ v out a? figure 35 . differential amplifier configuration table 7 . on - chip differential filter component values r in (k ?) r fb (k ?) r m (?) c s (pf) c fb (pf) c m (pf) optimal 4.75 3.01 43 8.2 47 33 to l e ran ce range 1 2.37 to 5.7 6 2.4 to 4.8 7 36 to 47 0 to 10 20 to 100 33 to 56 1 values shown are the acceptable toleranc es for each component when altered relative to the optimal values used to achieve the stated specifications of the device. the range of value s for each of the components in the differ - ential amplifier configuration is listed in table 7 . when using the differential amplifier to gain the input voltages to the required modulator input range , it is advisable to implement the gain function by changing r in and leaving r fb as the listed optimal value. the common - mode input at each of th e differential amplifier inputs (p in v in a+ and p in v in a ?) can range from ? 0.5 v dc to 2.2 v dc. the amplifier has a constant output common - mode voltage of 2.048 v, that is, v ref /2 , the requisite common mode voltage for the modulator input pins (v in + and v in ?). figure 36 shows the signal conditioning that occurs using the differential amplifier configuration detailed in ta ble 7 with a 2.5 v input signal to the differential amplifier. the amplifier in this example is biased around ground and is scaled to provide 3.168 v p- p ( ? 0.5 dbfs) on each modulator input with a 2.048 v common mode. 06518-122 0v +2.5v ?2.5v 0v +2.5v ?2.5v a b +3.632v +2.048v +0.464v +3.632v +2.048v +0.464v v in + v in ? figure 36 . differential amplifier signal conditioning to obtain maximum performance from the a d7764, it is advisable to drive the adc with differential signals. figure 37 shows how a bipolar, single - ended signal biased around ground can drive the AD7764 with the use of an external op amp, such as the ad8021 . diff amp r in r fb c fb r in r m r m c s r fb c fb v in ? v in v in + ad8021 2r 2r r 06518-026 c m figure 37 . single - ended - to - differential conversion
AD7764 rev. a | page 20 of 32 modulator input stru c ture the AD7764 employs a double - sampling front end, as shown in figure 38 . for simplicity, only the equivalent input circuitry for v in + is shown. the equivalent circuitry for v in ? is the same. cs2 cpb2 ss4 sh4 cpa ss2 sh2 cs1 cpb1 ss3 sh3 ss1 sh1 analog modulator v in + 06518-027 figure 38 . equivalent input circuit the ss1 and s s3 s ampling switches are driven by iclk, whereas the ss2 and ss4 sampling switches are driven by iclk cs1 . when iclk is high, the analog input voltage is connected to c s1. on the falling edge of iclk , the ss1 and ss3 switches open , and the analog input is sampled on cs1. similarly, when iclk is low, the analog input voltage is connected to cs2. on the rising edge of iclk, the ss2 and ss4 switches open, and the analog input is sampled on cs2. the cpa, cpb1 , and cpb2 capacitors represent parasitic capacitances that include the junction capacitances associated with the mos swit ches. table 8. equivalent component values cs2 cpa c pb 1/cpb 2 13 pf 13 pf 13 pf 5 pf driving the modulato r inputs directly the ad7765 can be configured so that the on - board differential amplifier can be disabled and the modulator can be driven directly using discrete amplifiers. this allows the user to lower the power dissipation. to power down the on board differential amplifier, the user issues a write to set the amp off bit in the control register to logic high (see figure 39 ). sco (o) control register address 0x0001 amp off mode data 0x0001 fsi (i) sdi (i) 32 t sco 06518-301 figure 39 . writing to the AD7764 control register turning off the on - board differential amplifier the AD7764 modulator inputs must have a common - mode voltage of 2.048 v and adhere to the amplitudes as described in the AD7764 input structure section. an example of a typical circuit to drive the AD7764 for applica - tions requiring excellent ac and dc performance is shown in figure 40 . either the ad8606 or ad8656 can be used to drive the AD7764 modulator inputs directly. best practice is to short the differential amplifier inputs to ground through the typical input resistors and leave the typical feedback resistors in place. 06518-302 1 v in a? 2 v out a+ r fb r in 3 v in a+ 4 v out a? r fb r in 6 v in + AD7764 5 v in ? u1 10k? 4.99k ? 51? 0 ? 10k? c2 2 2.048v u2 10k? 4.99k ? 51? 0 ? 10k? c1 2 1.024v ad8606 ad8655 ad8606 ad8655 analog input 1 1 ?0.5dbfs input signal as described in input structure section. 2 set c1 and c2 as required for application input bw and anti-alias requirement. figure 40 . driving the AD7764 modulator inputs directly from a single - ended source (on - board differential amplifier powered down)
AD7764 rev. a | page 21 of 32 AD7764 interface reading da ta t he AD7764 uses an spi - comp atible serial interface. the timing diagram in figure 2 shows how the AD7764 transmits its con - version results. the data read from the AD7764 is clocked out using the serial clock output ( sco ) . the sco frequency is half that of the mclk input to the AD7764. the conversion result output on the serial data output (sdo) line is framed by the frame synchronization output, fso table 9 . status bits during data read , which is sent logic low for 32 sco cycles. each bit of the new conversion result is clocked onto the sdo line on the rising sco edge and is valid on the falling sco edge. the 32 - bit result consists of the 24 data bits followed by five status bits followed further by three z eros. the five status bits are listed in table 9 and described below the table . d7 d6 d5 d4 d3 filter - settle ovr lpwr dec_rate 1 dec_rate 0 ? the f ilter - settle bit indicates whether the data output from the AD7764 is valid . after resetting the device (using the reset pin) or clearing the digital filter (using the ? the ovr ( o ver range) bit is described in the sync pin), the filter - settle bit goes logic low to indicate that the full settling time of the filter has not yet pass ed and that the data is not yet valid. the filter - settle bit also go es to zero when the input to the part has asserted the over range alerts. over r ange alerts section. ? the lpwr bit is set to logic high when the AD7764 is operating in low power mode . see the power modes section for further details. ? the dec_rate 1 and d ec_rate 0 bits indicate the decimation ratio used . table 10 is a truth t able for the decimation rate bits. table 10. decimation rate status bits decimate dec_rate 1 dec_rate 0 64 0 1 128 1 x 1 256 0 0 1 dont c are. if the dec_rate 1 bit is set to 1 , AD7764 is in d ecimate 128 mode. reading statu s and other register s the AD7764 features a ga in correction register, an over range register, and a read - only status register. to read back the contents of these registers, the user must first write to the control register of the device and set the bit that corresponds to the register to be read . the next read operation outputs t he contents of the selected register (on the sdo pin) instead of a conversion result. to ensure that the next read cycle contains the contents of the register written to, the write o per ation to that register must be completed a minimum of 8 t sco before the falling edge of fso t he , which indicates the start of the next read cycle. see figure 4 for further details. AD7764 registers section provides more information on the relevant bits in the control register . writing to t he AD7764 a write operation to t he AD7764 is shown in figure 3 . the serial writing operation is synchronous to the sco si gnal. the status of the frame sync hronization input, fsi , is checked on the falling edge of the sco signal. if the fsi line is low , then the first data bit on the serial data in (sdi) line is latched in on the next sco falling edge. set t he active edge of the fsi signal to occur at a position whe n the sco signal is high or low to allow setup and hold time s from the sco falling edge to be met. the width of the figure 3 fsi signal can be set to between 1 and 32 sco periods wide. a second , or subsequent , falling edge that occurs before 32 sco periods have elapsed is ignored. details the format for the serial d ata being written to the AD7764 through the sdi pin. thirty - two bits are required for a write operation. the first 16 bi ts are used to select the register address that the data being read is intended for . the second 16 bits contain the d ata for the selected register. writing to the a d7764 is allowed at any time , even while r eading a conversion result. note that , after writing to the devices, valid data is not output until after the settling time for the filter has elapsed. the filte r - settle status bit is asserted at this point to indicate that the filter ha s settled and that valid data is available at the output.
AD7764 rev. a | page 22 of 32 AD7764 functionality synchroniz ation the sync input to the AD7764 provides a synchronization function that allows the user to begin gathering samples of the analog front - end inp ut from a known point in time. the sync function allows multiple AD7764 device s, operated from the same master clock that use common sync and reset signals , to be synchronized so that each adc simultane ously updates its output register. note that all devices being synchro - nized must operate in the same power mode and at the same decimation rate. in the case of a system with multiple AD7764s, c onnect common mclk, sync and reset signals to each AD7764 . the AD7764 sync pin is polled by the falling edge of mclk. the AD7764 device goes into sync when an mclk falling edge senses that the sync input signal is logic low. at this point, the digital filter sequencer is reset to 0. the filter is held in a reset state (in sync mode) until the first mclk falling edge senses sync where possible, ensure that all transitions of to be logic high sync occur synchronously with the rising edge of mclk (that is, as far away as possible from the mclk falling edge, or decision edge). otherwise, abide by the timing specified in figure 41 , which excludes the sync keep rising edge from occurring in a 10 ns window centered around the mclk fallings edge. sync logic low for a minimum of four mclk periods. when the mclk falling edge senses that sync has returned to l ogic high, the AD7764 filters begin to gather input samples simultaneously. the fso 06518-303 mclk sync t s min 4 t mclk t s hold t s setup falling edges are also synchronized, allowing for simultaneous output of conversion data. figure 41. sync following a tim ing relative to mclk sync , the digital filter needs time to settle before valid data can be read from the AD7764. the user knows there is valid data on the sdo line by checking the filter - settle status bit (see d7 in ta ble 9) that is output with each conversion result. the time from the rising edge of sync over r ange alerts until the filter - settle bit asserts depends on the filter configuration used. see the theory of operation section and the values listed in table 6 for details on ca lcul ating the time until filter - settle asserts . note that the filter_settle bit is designed as a reac tionary flag to indicate when the conversion data output is valid. the AD7764 offers an overrange function in both a pin and status bit output. the over range alerts i ndicate when the voltage applied to the AD7764 modulator input pins exceeds the limit set in the overrange register, indicating that the vo ltage applied is approaching a level w here the modulator will be over ranged. to set this limit , the user must program the register. the default over range limit is set to 80% of the v ref voltage (see the AD7764 registers section) . the overrange pin output s logic high to alert the user that the modulator has s ampled an input voltage greater in magnitu de than the overrange limit as set in the overrange register. the overrange pin is set to logic high when the modulator samples an input above the overrange limit. after the input returns below the limit, the overrange pin return s to zero. the overrange pin is updated after the first fir filter stage. its output changes at the iclk/4 frequency. t he ovr status bit is output as b it d6 o n sdo during a data conversion and can be checked in the AD7764 s tatus r egister. this bit is less dynamic than the overrange pin output. it is updated on each conversion result outpu t; that is, the bit changes at the output data rate. if the modulator has sampled a voltag e input that exceeded the overrange limit during the process of gathering samples for a particular conversion result output, then the ovr bit is set to logic high. overrange pin output logic level high low ovr bit logic level high low output frequency of fir filter 1 = iclk/4 overrange limit overrange limit ob s olute input to AD7764 [(v in +) ? (v in ?)] output data rate (odr) (iclk/decimation rate t t 06518-016 figure 42 . overrange pin and ovr bit v s. a bsolute v oltage a pplied to the m odulator the output points from fir f ilter 1 in figure 42 are not drawn to scale relative to the o utput data ra te points. the fir f ilter 1 output is updated either 16, 32, or 64 faster than the outpu t data r ate , depending on t he decimation rate in operation .
AD7764 rev. a | page 23 of 32 power modes low power mode during p ower - up, the AD7764 defaults to operate in normal power mode. there is no register write required. the AD7764 also offers low power mode . to operate the device i n low power mode, t he user sets the lpwr bit in the control register to logic high (s ee figure 43 ). operating the AD7764 in low pow er mode has no impact on the output data rate or available bandwidth. sco (o) control register address 0x0001 low power mode data 0x0010 fsi (i) sdi (i) 32 t sco 06518-017 figure 43 . write scheme for low power mode reset / the AD7764 features a pwrdwn mode reset / pwrdwn pin. holding the input to this pin logic low p laces the AD7764 in power - down mode. all int ernal circuitry is reset. apply a reset pulse to the AD7764 after initial power - up of the device. the AD7764 reset pin is polled by the rising edge of mclk. the AD7764 device goes into reset when an mclk rising senses th e reset input signal to be logic low. AD7764 comes out of reset on the first mclk rising edge that senses reset the best practice is to ensure that all transitions of to be logic high. r eset occur synchronously with the falling edge of mclk; otherwise, adhere to the timing requirements shown in figure 44 . reset should be kept at logic low for a minimum of one mclk period for a valid reset to oc cur. in cases where multiple AD7764 devices are being synchronized using the sync pulse and in the case of daisy chaining multiple AD7764 devices, a common reset pulse must be provided in addition to the common 06518-304 mclk t r min 1 t mclk t r hold t r setup reset sync and mclk signals. figure 44. reset decimation rate pin timing synchronous to mclk the decimation rate of the AD7764 is selected using the dec_rate pin. ta ble 11 shows th e voltage input settings required for each of the three decimation rates. table 11. dec_rate pin settings decimate dec_rate pin max imum output data rate 64 dv dd 312.5 kh z 128 floating 156.25 kh z 256 gnd 78.125 kh z
AD7764 rev. a | page 24 of 32 daisy c hainin g daisy chaining allows numerous devices to use the same digital interface lines. this feature is especially useful for reducing component co unt and wiring connections, such as in isolated multiconverter applications or for systems with a limited i nterfacing capacity. data readback is analogous to clocking a shift register. when daisy chaining is used, all devices in the chain must operate in a common power mode and at a common decimation r ate. the block diagram in figure 45 shows how to connect devices to achieve daisy - chain functionality. figure 45 shows four AD7764 devices daisy - chained together with a common mclk signal applied. t h is can work in decimate 128 or decimate 256 mode only . reading data in daisy -c hain mode referring to figure 45 , note that t he sdo line of AD7764 (a) provides the output data from the chain of AD7764 converters . also, note that for the last device in the chain, AD7764 (d ), the sdi pin is conn ected to ground. all of the devices in the chain must use common mclk and sync to enable the daisy - chain conversion process, apply a common signals. sync after a pulse to all devices (see the synchroniz ation section). sync pulse is applied to all devices, the fil ter settling time must pass before the filter - settle bit is asserted , indicating valid conversion data at the output of the chain of devices. as shown in figure 46 , the first conversion result is output from the device labeled AD7764 (a). this 32 - bit conversion result is then followed by the conversion results from the AD7764 ( b), AD7764 ( c), and AD7764 (d) devices with all conv ersion results output in an msb - first sequence. the signals output from the daisy chain are the stream of conversion results from the sdo pin of AD7764 (a) and the fso signal output by the first device in the chain, AD7764 (a) . the falling edge of fso signals the msb of the first conversion output in the chain. fso the maximum number of devices that can be daisy - chained is dependent on the decimation rate selected . calculate the max imum number of devices that can be daisy - chained by simp ly dividing the cho sen decimation rate by 32 (the number of bits that must be clocked out for each conversion). stays logic low throughout the 32 sco clock periods needed to output the AD7764 (a) result and then goes logic high during the output of the conversion re sults from the AD7764 (b), AD7764 (c), and AD7764 (d devices . table 12 provides the maximum number of chained devices for each decimation r ate. table 12. maximum chain length for all decimation rates decimation rate maximum chain length 256 8 128 4 64 2 sync sdi fsi sdo mclk AD7764 (d) fsi sync mclk sync sdi fsi sdo mclk AD7764 (c) sync sdi fsi sdo mclk AD7764 (b) sync sdi fsi mclk AD7764 (a) sdo fso 06518-018 figure 45 . daisy chaining four devices in d ecimate 128 mode using a 40 mh z mclk s ignal sco fso (a) 32 t sco 32 t sco 32 t sco 32 t sco sdo (a) AD7764 (a) 32-bit output AD7764 (b) 32-bit output AD7764 (c) 32-bit output AD7764 (d) 32-bit output AD7764 (a) 32-bit output AD7764 (b) 32-bit output sdi (a) = sdo (b) AD7764 (b) AD7764 (c) AD7764 (d) AD7764 (b) AD7764 (c) sdi (b) = sdo (c) AD7764 (c) AD7764 (d) AD7764 (c) AD7764 (d) sdi (c) = sdo (d) AD7764 (d) AD7764 (d) 06518-019 figure 46 . daisy - chain mod e, data read t iming d iagram (for the daisy -c hain c onfiguration s hown in figure 45 )
AD7764 rev. a | page 25 of 32 writing data in dais y-c hain mode wr i ting to AD7764 devices in daisy - chain mode is similar to writing to a single device. the serial writing ope ration is syn - chronous to the sco signal. the st a tus of the frame sync hro - nization input, fsi , is checked on the falling edge of the sco signal. if the writing data to the AD7764 in daisy - chain mode operates with the same timing structure as writing to a single device (see fsi line is low , then the first d ata bit on the serial data in the s di line is latched in on the next sco falling edge. figure 3 ). the difference between writing to a single dev ice and writing to a number of daisy - chained devices is in the imple - mentation of the fsi signal. the number of devices that are in the daisy chain determines the period for which the fsi signal must remain logic low. to write to n number of devices in the daisy chain, the period between the falling edge of fsi and the rising edge of fsi must be between 32 (n ? 1) to 32 n sco periods. for example, if three AD7764 devices are being w ritten to in daisy - chain mode , fsi the AD7764 devices can be written to at any time. the falling edge of is logic low for between 32 (3 ? 1) to 32 3 sco pulses. this means that the rising edge of fsi must occur between the 64 th and 96 th sco period s. fsi overrides all attempts to read data from the sdo pin. in the case of a daisy chain , the fsi signal remaining logic low for more than 32 sco periods indicates to the AD7764 device that there are more devices further on in the ch ain. this means that the AD7764 direct s data that is input on the sdi pin to its sdo pin. this ensures that data is passed t o the next device in the chain. sync sdi fsi sdo mclk AD7764 (d) fsi sync mclk sync sdi fsi sdo mclk AD7764 (c) sync sdi fsi sdo mclk AD7764 (b) sync sdi fsi mclk AD7764 (a) sdo fso sco sdi 06518-020 figure 47 . writing to an AD7764 daisy -c hai n c onfiguration fsi sco sdi (d) sdi (c) = sdo (d) sdi (b) = sdo (c) sdi (a) = sdo (b) sdi (d) sdi (c) sdi (b) sdi (a) 32 t sco 32 t sco 32 t sco 31 t sco t 10 06518-021 figure 48 . daisy - chain write timing diagram ; writing to four AD7764 d evices
AD7764 rev. a | page 26 of 32 clocking the AD7764 the AD7764 requires an external low jitter clock source. this signal is applied to the mclk pin. an internal clo ck signal (iclk) is derived from the mclk input signal. the iclk controls the internal operation of the AD7764. the maximum iclk frequency is 20 mhz. t o generate t he iclk , iclk = mclk /2 for output data rates equal to those used in audio systems, a 12.288 mhz iclk frequency can be used. as shown in ta ble 6 , output data rates of 96 khz and 48 khz are achievable with this iclk frequency. mclk jitter requirem ents the mclk jitter requirements depend on a number of factors and are giv en by 20 )( 10 2 )( dbsnr f osr t in rms j = where: osr = oversampling ratio = f iclk /odr . f in = maximum input frequency. snr(db) = target snr. e xample 1 this example can be taken from table 6 , where : odr = 312.5 k hz. f iclk = 20 mhz. f in (max) = 1 56.25 khz . snr = 10 4 db. ps t rms j 41.51 101025.1562 64 2.53 )( = = this is the maximum allowable clock jitter for a full - scale, 1 56.25 khz input tone with the g iven iclk and output data r ate. e xample 2 this second example can also be taken from table 6 , where : odr = 48 khz. f iclk = 12.288 mhz. f in (max) = 19.2 khz. snr = 1 09 db. ps 470 10102.192 256 45 .53 )( = = rms j t the input amplitude also has an effect on these jitter figures. f or example, if the input level i s 3 db below full scale , the allow - able jitter is increased by a factor of 2 , increasing the first example to 144.65 ps rms . this happens when the maximum slew rate is decreased by a reduction in amplitude. figure 49 and figure 50 illustrate this po int , showing the maximum slew rate of a sine wave of the same frequency but with different amplitudes. 1.0 ?1.0 0.5 0 ?0.5 06518-022 figure 49 . maximum slew rate of a sine wave with an amplitude of 2 v p -p 1.0 ?1.0 0.5 0 ?0.5 06518-023 figure 50 . maximum slew rate of the same frequency sine wave as in figure 49 with an amplitude of 1 v p -p
AD7764 rev. a | page 27 of 32 d ecoupling and layout information supply decoupling the decoupling of the supplies applied to the AD7764 is important in achieving maximum perfor mance. each supply pin must be decoupled to the correct ground pin with a 100 nf, 0603 case size capacitor. pay particular attention to decoupling pin 7 (av dd 2 ) directly to t he nearest ground pin (p in 8) . the digital ground pin agnd2 (p in 20) is routed di rectly to ground. also, connect refgnd (p in 26 ) directly to ground. the dv dd (pin 17) and av dd 3 (p in 28) supplies should be decoupled to the ground plane at a point away from the device. it is a d vised to decouple the supplies that are connected to the foll owing supply pins through 0603 size, 100 nf capacitors to a star ground point linked to p in 23 (agnd 1): ? v ref + ( pin 27) ? av dd 4 ( pin 25) ? av dd 1 ( p in 24) ? av dd 2 ( p in 21) a l ayout decoupling scheme for these supplies , which connect to the right side of the AD7764 , is shown in figure 51 . note the star - point ground created at p in 23. 06518-133 av dd 2 (pin 21) v ref + (pin 27) gnd pin 23 star-point gnd av dd 4 (pin 25) av dd 3 (pin 28) via to gnd from pin 20 av dd 1 (pin 24) gnd pin 15 figure 51 . supply decoupling reference voltage fi ltering a low noise reference source, such as the adr4 44 or adr 4 34 (4.096 v), is suitable for use with the ad776 4 . the reference voltage supplied to the ad776 4 s hould be decoupled and filtered as shown in figure 52 . the recommended scheme for the reference voltage supply is a 2 00 series resistor connected to a 100 f tantalum capacitor, followed by a 10 nf decoupling capacitor very close to the v ref + pin . 06518-134 7.5v v out 2 v in 6 4 10f 100nf + 100nf + adr444 gnd v ref + pin 27 100f 200? figure 52 . reference connection differential amplifi er components the components recommended f or use around the on -chip differential amplifier are detailed in table 7 . matching the components on both sides of the differential amplifier is important to minimize distortion of the signal applied to the amplifier. a tolerance of 0.1% or better is required for these components. symmetrical routing of the tracks on both sides of the differential amplifier also assists in achieving stated perfor m ance. figure 53 shows a typical layout for the com - ponents around the differential amplifier. note that the traces for both differential paths are made as symmetrical as possible and that the feedback resistors and capacitors are placed on the underside of the pcb to enable the simplest routing. 06518-135 r fb c fb r in r in v in a? v in a+ figure 53 . typical layout structure for surrounding components layout consideration s wh ereas using the correct components is essential to achieve opti mum performance, the correct layout is equally as impor tant . the AD7764 product page on www.analog.com contains the g erber files for the AD7764 evaluation board. the gerber files should be used as a reference when desig ning any system using the AD7764 . the use of ground planes should be carefully considered. to ensure that the return currents through the decoupling capacitors are flowing to the correct ground pin, the ground side of the capacitors should be as close to the ground pin associated with that supply , as recommend ed in the supply decoupling section .
AD7764 rev. a | page 28 of 32 using t he AD7764 step1 through step 5 detail the sequence for p owering up and using the AD7764. 1. apply p ower to the device. 2. apply the mclk signal . 3. take reset low for a minimum of one mclk cycle , preferably synchro nous to the falling mclk edge. if multiple parts are to be synchronized, apply a common 4. wait a minimum of two mclk cycles after reset to all devices . reset 5. if multiple parts are being synchronized, a is released. sync pulse must be applied to the parts, preferably synchronous with the mclk rising edge. in the case where devices are not being synchronized, no sync pulse is required; a logic high signal should simply be applied to the sync when a pply ing the pin. sync ? the issue of a pulse , sync ? ensure that the pulse to the device must not coincide with a write to the device . sync data can then be read from the device using the default gain and over range threshold values. the conversion data read is not valid , however , until the settling time of the filter has elapsed . once this has occu rred, the filter - settle status bit is set , indicating that the data is valid. values for gain and over range thresholds can be written to or read from the respective registers at this stage. pulse is taken low for a minimum of four mclk periods . bias resistor select ion the AD7764 requires a resistor to be connected between the r bia s and agnd x pins . the resistor value should be selected to give a current of 25 a through the resistor to ground. for a 4.096 v reference voltage, the correct resistor value is 160 k?.
AD7764 rev. a | page 29 of 32 AD7764 registers the AD7764 has a number of us er - programmable registers . the control register is used to set the functionality of the on - chip buffer and differential amplifier and provides the option to power down the AD7764. there are also digital gain and over range threshold registers. writing to th ese registers involves writing the register address followed by a 16 - bit d ata - word. the register addresses, details of individual bits, and default values are provided in this section. control register table 13. control register ( a ddress 0x0001, default value 0x 0000) msb lsb d15 d14 d13 d12 d11 d10 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 0 rd ovr rd gain 0 rd stat 0 sync 0 b y pass ref 0 0 0 pwr down lpwr ref buf off amp off table 14. bit descriptions o f control register bit mnemonic comment 14 rd ovr 1 , 2 read o verrange. if this bit is set, the next read operation outputs the contents of the overrange threshold register i nstead of a conversion result. 13 rd gain read g ain. if this bit is set, the ne x t read operation output s the contents of the digit al gain re gister. 11 rd stat read s tatus. if this bit is set, the next read operation output s the contents of t he status regist er. 9 sync syn chronize. setting this bit initiate s a n internal synchronizati on routine. setting this bit simultan eously on multiple devices synchronize s all filters. 7 by pass ref bypass r eference . setting this bit bypasses the reference buffer if the buffer is off. 3 pwr down power -d own. a logic high powers the device down witho ut resetting. writing a 0 to this bit powers the device back up. 2 lpwr low p ower m ode. set to logic 1 when AD7764 is i n low power m ode. 1 ref buf off reference b uffer o ff. asserting this bit powers down the reference buffer. 0 amp off amplifier o ff. as serting this bit switches the differential amplifier off. 1 bit 14 to bit 11 and bit 9 are self - clearing bits. 2 only one of the bits can be set in any write op eration because it determines the contents of the next read operation. status register table 15 . status register (read only) msb lsb d15 d14 d13 d12 d11 d10 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 par t no 1 0 0 0 filter - settle 0 ovr 0 1 0 ref buf on amp on lpwr dec 1 dec 0 table 16. bit descriptions of the status register bit mnemonic comment 15 par tno part n umbe r. this bit is set to 1 for the AD7764. 10 filter - settle filter s ettling b it. this bit corresponds to the filter - settle bit in the status word output in the second 16 - bit read operation. it indicates when data is valid. 9 0 zero. this bit is set to logic 0 . 8 ovr overrange. if the current analog input exceeds the current overrange threshold, this bit is set. 4 ref buf on reference b uffer o n. this bit is set when the reference buffer is in use. 3 amp on amplifier o n. this bit is set when the input amplifier is in use. 2 lpwr low power mode. this bit is set when operating in low power mode. 1 to 0 dec _ rate [ 1:0 ] decimation r ate. these bits correspond to the decimation rate in use.
AD7764 rev. a | page 30 of 32 gain register address 0 x 0004 non - bit - mapped, default value 0xa000 the gain regi ster is scaled such that 0x8000 corresponds to a gain of 1.0. the default value of this regist er is 1.25 (0xa000). this results in a full - scale digital output when the input is at 80% of v ref + , tying in with the maximum analog input range of 80% of v ref + p-p . overrange register address 0 x 0005 non - bit - mapped , default value 0xcccc the o ver r ange re gister value is compared with the output of the first decimation filter to obtain an overload indication with minimum propagation delay. this is prior to any g ain scaling . the default value is 0xcccc , which corre sponds to 80% of v ref + (the maximum permit ted analog input voltage) . assuming v ref + = 4.096 v, the bit is then set when the input voltage exceeds approximately 6.55 v p-p differential . the over - range bit is set immediately if the analog input voltage exceeds 100% of v ref + for more than four consec utive samples at the modulator rate .
AD7764 rev. a | page 31 of 32 outline dimensions compliant to jedec standards mo-153-ae 28 15 14 1 8 0 seating plane coplanarity 0.10 1.20 max 6.40 bsc 0.65 bsc pin 1 0.30 0.19 0.20 0.09 4.50 4.40 4.30 0.75 0.60 0.45 9.80 9.70 9.60 0.15 0.05 figure 54. 28 - lead thin shrink small outline [tssop ] ( ru - 28 ) dimensions shown in millimeters ordering guide model temperature range package description package option AD7764bruz 1 C 40c to +85c 28- lead thin shrink small outline [tssop] ru - 28 AD7764bruz - reel7 1 C 40c to +85c 28- lead thin shrink small outline [tssop] ru - 28 eval - AD7764e dz 1 evaluation board 1 z = rohs compliant part.
AD7764 rev. a | page 32 of 32 notes ? 2007 - 2009 analog devices, inc. all rights reserved. trademarks and registered trademarks are the property of their respective owners. d 06518 -0- 11 / 09(a)

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